74HC73 DUAL JK FLIP FLOP

High speed CMOS recommend for High speed CMOS recommend for all new designs. Static sensitall new designs. Static sensitive . Required light decouplinive . Required light decoupling (0.1µF per 20 ICs) With 75-8g (0.1µF per 20 ICs) With 75-80% power reduction compared to0% power reduction compared to standard Schottky. - Tri-S standard Schottky. - Octaltate Quad D Register Transparent Latch (3 State) Weight: 0.0010 kg